Research on Failures and Mechanisms Caused by Wire Bonding Damage to Devices

Abstract:

This paper explains the basic concepts of the wire bonding process and discusses bonding damage caused by improper bonding process conditions or material selection issues. Through wet chemical etching tests, the original damage morphology caused by improper bonding on the chip can be exposed. Taking a heavy aluminum wire bonded MOSFET device as an example, the paper introduces the differences in impact on device performance for three types of bonding damage: Type I does not affect device reliability; Type II causes minor damage to the bonding pad metal and substrate material, potentially leading to channel integrity disruption, increased device leakage, reduced reverse breakdown voltage, and other functional degradation, requiring failure risk management through means such as destructive physical analysis; Type III has already resulted in chip burnout and functional failure. For this type of damage, through chip front-side and cross-sectional morphology analysis, the characteristics of the burnout failure are revealed. Finally, corresponding improvement measures are proposed for different damage types. This research provides an analytical method for identifying and preventing bonding damage and holds reference value for improving power device reliability and process optimization.

Introduction:

Wire bonding refers to the connection of metal wires (e.g., Au, Al, Cu) to chip bonding pads under the combined action of ultrasound, heat, and pressure, thereby achieving electrical interconnection between the chip and external pins [1-2]. Bonding damage is a phenomenon where, due to improper process conditions or material selection during the bonding process, the bonding pad metal or underlying substrate material of the chip is damaged. It is a manufacturing process defect [3-4]. Improper process conditions mainly include excessively high parameters such as ultrasound, heat, or pressure, or misalignment between the bond wire and the bonding pad. Material issues include oxidation of the bond wire, excessively hard material; oxidation of the pad metal, insufficient thickness, or surface contamination, etc. [5-6].

Severe bonding damage is often referred to as "cratering" and is commonly seen in copper wire bonded devices. Due to the high hardness of copper wire, a relatively high bonding force is often required during bonding to ensure connection quality. Some devices using heavy aluminum wire bonding may also experience damage to the pad metal or even the underlying substrate due to improper process parameters, such as aluminum extrusion or cracks, thereby affecting the chip's internal structure and leading to functional failure. Insufficient bonding force may lead to a cold joint or wire lift-off; even if immediate lift-off does not occur, intermetallic compounds may form at the interface during long-term electrical operation (common in dissimilar material bonding), eventually still causing lift-off issues [7-8].

This paper selects a certain model of high-power N-channel enhancement-mode Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) device (cross-section shown in Figure 1) to study the impact of three different degrees of bonding damage on device performance.

1. Bonding Damage Test Method

Bonding damage or craters are located on the bonding pad beneath the bond point and are typically obscured by the bond point itself. Therefore, observing their morphology requires first removing the bond wire, then inspecting the metal layer or substrate material under a metallographic microscope or scanning electron microscope. To preserve the original damage morphology as much as possible, wet chemical etching is often used to remove the bond wire [9]. Bond wire materials typically include Au, Al, Si-Al, Cu, etc., while the top metal of the bonding pad is generally Au or Al. Therefore, common bonding combinations include Au-Au, Au-Al, Al-Al, Al-Au, Cu-Al, Cu-Au, etc. Table 1 lists etchants and their formulations for different metals. Selecting the appropriate etchant allows for the sequential removal of the bond wire and the bonding pad metal material [10].

2. Impact of Different Types of Bonding Damage on Devices

The degree of damage caused by improper bonding to devices varies. The following discussion takes a certain model of high-power N-channel enhancement-mode MOSFET device as an example. The source of this device uses 2 heavy aluminum wires bonded to the chip's aluminum metallization layer.

2.1. Impact of Bonding Damage Type I on Devices

Figure 2a shows the chip morphology after decapsulation, indicating the use of 2 heavy aluminum wires for bonding. Each wire has a first bond and a second bond point on the chip. Figure 2b shows the morphology after removing the bond wires and the chip's top metal layer using wet chemical etching. A slight bonding tail mark can be seen at the bond point on the chip surface. The device performed normally in functional tests and I-V tests. Strictly speaking, this situation does not constitute actual bonding damage and does not affect device reliability.

2.2. Impact of Bonding Damage Type II on Devices

Figure 3a shows the morphology after device decapsulation; no obvious cracks or damage are visible on the chip surface. Figure 3b shows the morphology after removing the bond wires and all metalization layers on the chip surface; damage to the substrate material (silicon) caused by bonding is visible. Magnification of the second bond point reveals scratches, collapse, and other phenomena on the silicon surface, as shown in Figures 3c-3d.

The source and drain of a MOSFET device are N+ regions formed by heavy doping on a P-type substrate. During operation, a conductive channel is formed between source and drain due to carrier diffusion. If the source/drain region material is damaged, the integrity of the channel is disrupted at the microscopic level, hindering carrier diffusion; macroscopically, this manifests as increased device leakage current and reduced reverse breakdown voltage, leading to functional degradation.

The device's functional and I-V test results still appeared normal, making it difficult to effectively screen out during the electrical testing phase. However, during long-term power-on operation, device leakage may gradually increase, performance may progressively degrade, affecting long-term reliability. Such potential risks can be identified and controlled through means such as destructive physical analysis.

2.3. Impact of Bonding Damage Type III on Devices

Figure 4a shows the morphology after device decapsulation. A burn-through hole is visible at the second bond point of the lower-left bond wire. Figure 4b shows the morphology after removing the bond wire and the chip's top metalization layer. An elliptical bonding damage mark is present at the first bond point, with part of the substrate (Si) already exposed at the damage site; cracks accompany the metal at the damage edge. Figure 4c shows a magnified view of this point. The edge of the burn-through hole at the second bond point appears molten, the hole is deep, cracks are also present in the metalization layer around the hole, and the cracks extend to the chip edge. Figure 4d shows a magnified view of the hole. The results of composition analysis inside the hole are shown in Figure 4e, containing Si, Al, Cu, and O. Device I-V testing showed short circuits between source-drain, source-gate, and drain-gate.

Bonding damage causes the device's leakage to increase continuously during long-term use, ultimately leading to chip burnout due to over-power. During burnout, local temperatures are extremely high, materials form solid solutions, and Si has a certain solubility in Al (eutectic temperature is 577 °C), promoting Si diffusion into Al, ultimately forming holes.

The cross-sectional morphology of the first bond point is shown in Figure 5. It can be seen that bonding damage led to cracks and fragmentation of the substrate material at locations ①, ②, and ③.

The cross-sectional morphology at the second bond point is shown in Figure 6. It can be seen that the hole at location ③ has penetrated vertically through the chip. This also verifies that the Cu element found in the composition analysis inside the hole in Figure 4 originated from the chip's substrate material. It is worth noting that voids exist in the adhesive layer between the chip and the substrate, as shown at location ①. Composition analysis at location ③ to the left of the hole revealed only Al and Si elements, indicating that location ③ is also an adhesive void area; the Al-Si solid solution diffused to this location after chip burnout. If adhesive voids exist between the chip and the substrate, heat generated during device operation cannot be effectively dissipated, and long-term power-on operation can also lead to chip burnout.

2.4. Improvement Measures for Bonding Damage

a) Optimize Bonding Process

This type of device uses Al-Al homogeneous bonding, where both the bond wire and the bonding pad material are Al. Ultrasonic wedge bonding is typically used. The bonding pressure, temperature, time, and power can be appropriately adjusted during the bonding process to reduce the risk of bonding pad damage and cracks.

b) Optimize Interface Material Structure

Increase the thickness of the aluminum buffer layer in the chip bonding pad to release residual stress generated by bonding and reduce the risk of indentations and cracks.

c) Ensure Environmental Cleanliness

Maintain cleanliness in bonding equipment and process areas, especially ensuring the flatness and cleanliness of the bonding interface to reduce ionic contamination at the interface.

3. Conclusion

This paper has elaborated on the basic concepts of the wire bonding process and the bonding damage issues caused by improper process conditions or material selection. Through wet chemical etching tests, the original damage morphology on the chip caused by improper bonding can be exposed. Taking a heavy aluminum wire bonded MOSFET device as an example, the impact of three different types of bonding damage on device performance was discussed. Bonding Damage Type I does not affect device reliability. Bonding Damage Type II causes minor damage to the chip's bonding pad metal and substrate material: microscopically, it disrupts channel integrity and hinders carrier diffusion; macroscopically, it manifests as increased leakage, reduced reverse breakdown voltage, and functional degradation. Although device functional and I-V test results may be normal, making it difficult to screen out during electrical testing, leakage may further increase and performance degrade during long-term power-on operation, affecting long-term reliability. Failure risk management for such devices through means like destructive physical analysis is necessary. Bonding Damage Type III resulted in chip burnout and functional failure; the paper described in detail the damage morphology on the chip's front side and cross-section. Finally, corresponding improvement measures were proposed for the bonding damage issue.